VCVTPH2QQ - ConVerT Packed Half to Qword Qword
FP16 -> signed QWORD
rounding controlled by {er} or MXCSR
VCVTPH2QQ xmm1{k1}{z}, xmm2/m32/m16bcst (V5+FP16+VL
__m128i _mm_cvtph_epi64(__m128h a)
__m128i _mm_mask_cvtph_epi64(__m128i s, __mmask8 k, __m128h a)
__m128i _mm_maskz_cvtph_epi64(__mmask8 k, __m128h a)
VCVTPH2QQ ymm1{k1}{z}, xmm2/m64/m16bcst (V5+FP16+VL
__m256i _mm256_cvtph_epi64(__m128h a)
__m256i _mm256_mask_cvtph_epi64(__m256i s, __mmask8 k, __m128h a)
__m256i _mm256_maskz_cvtph_epi64(__mmask8 k, __m128h a)
VCVTPH2QQ zmm1{k1}{z}, xmm2/m128/m16bcst{er} (V5+FP16
__m512i _mm512_cvtph_epi64(__m128h a)
__m512i _mm512_mask_cvtph_epi64(__m512i s, __mmask8 k, __m128h a)
__m512i _mm512_maskz_cvtph_epi64(__mmask8 k, __m128h a)
__m512i _mm512_cvt_roundph_epi64(__m128h a, int r)
__m512i _mm512_mask_cvt_roundph_epi64(__m512i s, __mmask8 k, __m128h a, int r)
__m512i _mm512_maskz_cvt_roundph_epi64(__mmask8 k, __m128h a, int r)
x86/x64 SIMD Instruction List
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