VCVTUDQ2PH - ConVerT Unsigned DoubleQword to Packed Half
unsigned DWORD -> FP16
VCVTUDQ2PH xmm1{k1}{z}, xmm2/m128/m32bcst (V5+FP16+VL
__m128h _mm_cvtepu32_ph(__m128i a)
__m128h _mm_mask_cvtepu32_ph(__m128h s, __mmask8 k, __m128i a)
__m128h _mm_maskz_cvtepu32_ph(__mmask8 k, __m128i a)
VCVTUDQ2PH xmm1{k1}{z}, ymm2/m256/m32bcst (V5+FP16+VL
__m128h _mm256_cvtepu32_ph(__m256i a)
__m128h _mm256_mask_cvtepu32_ph(__m128h s, __mmask8 k, __m256i a)
__m128h _mm256_maskz_cvtepu32_ph(__mmask8 k, __m256i a)
VCVTUDQ2PH ymm1{k1}{z}, zmm2/m512/m32bcst{er} (V5+FP16
__m256h _mm512_cvtepu32_ph(__m512i a)
__m256h _mm512_mask_cvtepu32_ph(__m256h s, __mmask16 k, __m512i a)
__m256h _mm512_maskz_cvtepu32_ph(__mmask16 k, __m512i a)
__m256h _mm512_cvt_roundepu32_ph(__m512i a, int r)
__m256h _mm512_mask_cvt_roundepu32_ph(__m256h s, __mmask16 k, __m512i a, int r)
__m256h _mm512_maskz_cvt_roundepu32_ph(__mmask16 k, __m512i a, int r)
x86/x64 SIMD Instruction List
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